APR综述|概率自旋逻辑计算中的p-比特

文章链接：https://doi.org/10.1063/1.5055860

三端p-bit

摘要

我们介绍了一种介于数字电子学的标准比特和量子计算的新兴q比特之间的p比特的概念。我们表明，低势垒磁体（Low barrier magnets，LBM）为p比特提供了一种自然的物理表示，并且可以由设计为接近面内过渡的垂直磁体或圆形面内磁体构建。使用LBMs作为自由层构建的磁隧道结(MTJs)可以与标准NMOS晶体管结合，为大规模概率电路提供三端构件，可设计用于执行有用的功能。有趣的是，这个三端单元看起来就像嵌入式磁随机存取存储器技术中使用的1T/MTJ设备，除了一个区别:MTJ自由层使用了LBM。我们希望，p比特和p电路的概念将有助于为这一新兴技术开辟新的应用空间。虽然p比特可以不需要涉及MTJ;任何波动电阻都可以与晶体管结合来实现它，而使用传统CMOS技术的完全数字实现也是可能的。p-bit还在随机机器学习和量子计算这两个活跃但互不相干的研究领域之间提供了概念上的桥梁。首先，有些应用是基于p比特与二进制随机神经元(BSN)的相似性，这是机器学习中一个众所周知的概念。三端p比特可以为BSN提供一种有效的硬件加速器。其次，有一些应用是基于p比特就像简化版的q比特。基于SPICE模拟的初步演示表明，包括量子退火在内的几个优化问题都适用于在室温下使用现有技术按比例放大的p-bit实现。

We introduce the concept of a probabilistic or p-bit, intermediate between the standard bits of digital electronics and the emerging q-bits of quantum computing.We show that low barrier magnets or LBMs provide a natural physical representation for p-bits and can be built either from perpendicular magnets designed to be close to the in-plane transition or from circular in-plane magnets. Magnetic tunnel junctions (MTJs) built using LBMs as free layers can be combined with standard NMOS transistors to provide three-terminal building blocks for large scale probabilistic circuits that can be designed to perform useful functions. Interestingly, this three-terminal unit looks just like the 1T/MTJ device used in embedded magnetic random access memory technology, with only one difference: the use of an LBM for the MTJ free layer. We hope that the concept of p-bits and p-circuits will help open up new application spaces for this emerging technology. However, a p-bit need not involve an MTJ; any fluctuating resistor could be combined with a transistor to implement it, while completely digital implementations using conventional CMOS technology are also possible. The p-bit also provides a conceptual bridge between two active but disjoint fields of research, namely, stochastic machine learning and quantum computing. First, there are the applications that are based on the similarity of a p-bit to the binary stochastic neuron (BSN), a well-known concept in machine learning. Three-terminal p-bits could provide an efficient hardware accelerator for the BSN. Second, there are the applications that are based on the p-bit being like a poor man’s q-bit. Initial demonstrations based on full SPICE simulations show that several optimization problems, including quantum annealing are amenable to p-bit implementations which can be scaled up at room temperature using existing technology.